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r1ex25002asa00a/r1ex25004asa00a r1ex25002ata00a/r1ex25004ata00a serial peripheral interface 2k eeprom (256-word 8-bit) 4k eeprom (512-word 8-bit) electrically erasable and progr ammable read only memory rej03c0357-0002 preliminary rev.0.02 jan.14.2009 description r1ex25xxx series is the serial peripheral interface co m p atible (spi) eeprom (electrically erasable and pro g r am m a b l e rom). it realizes h i g h sp eed , lo w p o w er co n s u m p tio n an d a h i g h lev e l o f reliab ility b y em p l o y in g advanced m onos m e m o ry t echnol ogy and cm os process and l o w vol t a ge ci rcui t r y t echnol ogy . it al so has a 16-by t e page program m i ng funct i on t o m a ke i t ? s wri t e operat i on fast er. not e : r e nesas technol ogy ?s seri al eepr o m are aut hori zed fo r usi ng consum er appl i cat i ons such as cel l u l a r phones, cam corders, audi o equi pm ent s . therefore, pl ease c ont act r e nesas technol ogy ?s sal e s offi ce before usi ng i ndust r i a l appl i cat i ons such as aut o m o t i v e sy st em s, em bedded cont rol l e rs, and m e t e rs. features ? si ngl e suppl y : 1.8 v t o 5.5 v ? serial peripheral interface com p atible (spi bus) ? spi m ode 0 (0,0), 3 (1,1) ? c l ock frequency : 5 m h z (2.5 v t o 5.5 v), 3 m h z (1.8 v t o 5.5 v) ? power di ssi pat i on: ? st andby : 2 a (m ax) ? active (read): 2 m a (m ax) ? active (w rite): 2.5 m a (m ax) ? au to m a tic p a g e write: 1 6 - b y te/p ag e ? w r ite cycle tim e: 5 m s ? endurance: 1,000k c y cl es @ 25 c ? dat a ret e nt i on: 100 years @ 25 c ? sm all size packages: sop-8pin, tssop-8pin ? shi ppi ng t a pe and reel ? tssop-8pi n: 3,000 ic / r eel ? sop-8pi n : 2,500 ic / r eel ? tem p erature range: ? 40 t o + 85 c ? lead free product . prel i m i n ary : the speci fi cat i ons of t h i s devi ce are subject t o change wi t hout not i ce. pl ease cont act y our nearest r e nesas technol ogy ' s sal e s dept . regardi ng speci fi cat i ons rej03c0357-0002 rev. 0.02 jan.14 .2009 page 1 of 20
r1ex25002axx00a/r1ex25004axx00a rej03c0357-0002 rev. 0.02 jan.14 .2009 page 2 of 20 ordering information t y p e no . in tern al o r g a n i zatio n op eratin g v o ltag e f req u e n c y packag e r1ex 2 5 0 0 2 a s a 0 0 a 2 - k b i t (256 8-bit) 1.8 v to 5.5 v 5 mhz (2.5 v to 5.5 v) r1ex 2 5 0 0 4 a s a 0 0 a 4 - k b i t (512 8-bit) 3 mhz (1.8 v to 5.5v) 150mil 8-pin plastic sop prsp0008df - b (fp-8dbv) lead free r1ex25002at a 0 0 a 2 - k b i t (256 8-bit) 1.8 v to 5.5 v 5 mhz (2.5 v to 5.5 v) r1ex25004at a 0 0 a 4 - k b i t (512 8-bit) 3 mhz (1.8 v to 5.5 v) 8-pin plastic t ssop pt sp0008jc-b ( ttp - 8 d a v ) lead free pin arrangement 8-pin sop/tssop (t op view) 1 2 3 4 8 7 6 5 v cc hold c d s q w v ss pin description pin na me func tion c s e r i a l c l o c k d serial data input q serial data output s chip select w w r ite protect hold hold v cc s u p p l y v o l t a g e v ss g r o u n d
r1ex25002axx00a/r1ex25004axx00a rej03c0357-0002 rev. 0.02 jan.14 .2009 page 3 of 20 block diagram high voltage generator memory array y -select & sense amp. serial-parallel converter address generator control logic y decoder x decoder v cc v ss s w c hold d q absolute maximum ratings p a r a m e t e r s y m b o l v a l u e u n i t supply voltage relative to v ss v cc ? + ? * 2 to +7.0 * 3 v operating tem perature range * 1 t o p r ? + ? + ? + dc operating conditions pa ra me te r s y m b o l m i n ty p ma x u n i t supply voltage v cc 1 . 8 ? ? + * 2 v v il ? * 1 ? ? ? + ? + + s , w ,hold ) c i n * 1 ? ? * 1 ? ? % notes: 1. not 100 % tes t ed.
r1ex25002axx00a/r1ex25004axx00a rej03c0357-0002 rev. 0.02 jan.14 .2009 page 4 of 20 dc characteristics pa ra me te r s y m b o l m i n ma x u n i t te s t c onditions input leakage current i li 2 a v cc = 5.5 v, v in = 0 to 5.5 v ( s , d, c, hold , w ) output leakage current i lo 2 a v cc = 5.5 v, v out = 0 to 5.5 v (q) v cc current standby i sb 2 a v in = v ss or v cc , v cc = 5.5 v a c t i v e i cc1 2 m a v cc = 5.5 v, read at 5 mhz v in = v cc 0.1/v cc 0.9 q = open i cc2 2 . 5 m a v cc = 5.5 v, w r ite at 5 mhz v in = v cc 0.1/v cc 0.9 output voltage v ol1 0 . 4 v v cc = 5.5 v, i ol = 2 ma v ol2 0 . 4 v v cc = 2.5 v, i ol = 1.5 ma v oh1 v cc 0.8 v v cc = 5.5 v, i oh = ? 2 ma v oh2 v cc 0.8 v v cc = 2.5 v, i oh = ? 0.4 ma
r1ex25002axx00a/r1ex25004axx00a rej03c0357-0002 rev. 0.02 jan.14 .2009 page 5 of 20 ac characteristics test conditions ? input pul es l e vel s : v il = v cc 0.2 v ih = v cc 0.8 ? input ri se and fal l t i m e: 10 ns ? input and out put t i m i ng reference l e vel s : v cc 0.3, v cc 0.7 ? ou tp u t referen ce lev e ls: v cc 0.5 ? out put l o ad: 100 pf (ta = ? 40 t o + 85 c, v cc = 2.5 v t o 5.5 v) p a r a m e t e r s y m b o l a l t m i n m a x u n i t n o t e s clock frequency f c f sc k 5 m h z s active setup time t slc h t c ss1 9 0 n s s not active setup time t s hch t c ss2 9 0 n s s deselect time t sh sl t cs 9 0 n s s active hold time t chs h t cs h 9 0 n s s not active hold time t chs l 9 0 n s clock high time t ch t cl h 9 0 n s 1 clock low time t cl t cl l 9 0 n s 1 clock rise time t cl ch t rc 1 s 2 clock fall time t chcl t fc 1 s 2 data in setup time t dv ch t ds u 2 0 n s data in hold time t chdx t dh 3 0 n s clock low hold time after hold not active t hhch 7 0 n s clock low hold time after hold active t hl ch 4 0 n s clock high setup time before hold active t chhl 6 0 n s clock high setup time before hold not active t chhh 6 0 n s output disable time t sh qz t dis 1 0 0 n s 2 clock low to output valid t cl qv t v 7 0 n s output hold time t cl qx t ho 0 n s output rise time t qlqh t ro 5 0 n s 2 output fall time t qhql t fo 5 0 n s 2 hold high to output low - z t hhqx t lz 5 0 n s 2 hold low to output high-z t hl qz t hz 1 0 0 n s 2 write time t w t wc 5 m s notes: 1. t ch + t cl 1/f c 2. not 100 % tested.
r1ex25002axx00a/r1ex25004axx00a rej03c0357-0002 rev. 0.02 jan.14 .2009 page 6 of 20 (ta = ? 40 t o + 85 c, v cc = 1.8 v t o 5.5 v) p a r a m e t e r s y m b o l a l t m i n m a x u n i t n o t e s clock frequency f c f sc k 3 m h z s active setup time t slc h t c ss1 1 0 0 n s s not active setup time t s hch t c ss2 1 0 0 n s s deselect time t sh sl t cs 1 5 0 n s s active hold time t chs h t cs h 1 0 0 n s s not active hold time t chs l 1 0 0 n s clock high time t ch t cl h 1 5 0 n s 1 clock low time t cl t cl l 1 5 0 n s 1 clock rise time t cl ch t rc 1 s 2 clock fall time t chcl t fc 1 s 2 data in setup time t dv ch t ds u 3 0 n s data in hold time t chdx t dh 5 0 n s clock low hold time after hold not active t hhch 1 4 0 n s clock low hold time after hold active t hl ch 9 0 n s clock high setup time before hold active t chhl 1 2 0 n s clock high setup time before hold not active t chhh 1 2 0 n s output disable time t sh qz t dis 2 0 0 n s 2 clock low to output valid t cl qv t v 1 2 0 n s output hold time t cl qx t ho 0 n s output rise time t qlqh t ro 1 0 0 n s 2 output fall time t qhql t fo 1 0 0 n s 2 hold high to output low - z t hhqx t lz 1 0 0 n s 2 hold low to output high-z t hl qz t hz 1 0 0 n s 2 write time t w t wc 5 m s notes: 1. t ch + t cl 1/f c 2. not 100 % tested.
r1ex25002axx00a/r1ex25004axx00a rej03c0357-0002 rev. 0.02 jan.14 .2009 page 7 of 20 timing waveforms serial input timing s c t chsl t slch t chdx t clch t chcl t shch t chsh t shsl t dvch msb in lsb in d q high impedance hold timing t chhl s hold c d q t hlch t chhh t hlqz t hhqx t hhch output timing s c d q lsb out addr lsb in t qlqh t qhql t shqz t ch t cl t clqv t clqx t clqv t clqx
r1ex25002axx00a/r1ex25004axx00a rej03c0357-0002 rev. 0.02 jan.14 .2009 page 8 of 20 pin function serial data output (q) thi s out put si gnal i s used t o t r ansfer dat a seri al l y out of t h e devi ce. dat a i s shi f t e d out on t h e fal l i ng edge of seri al cl ock (c ). serial data input (d) this input signal is used to transfer data serially into the device. it receives in structions, addresses, and the data to be written . valu es are latch e d o n th e risin g ed g e o f serial clo c k (c). serial clock (c) this input signal provides the tim ing of the serial interface. instructions, addresses, or data present at serial data input (d) are l a t c hed on t h e ri si ng edge of seri al cl ock (c ). dat a on seri al dat a out put (q) changes aft e r t h e fal l i ng edge of serial clock (c). chip select ( s ) w h en t h i s i nput si gnal i s hi gh, t h e devi ce i s desel ect ed and seri al dat a out put (q) i s at hi gh i m pedance. unl e ss an internal write cycle is in progre ss, the device will be in the standby m ode. driving chip select ( s ) lo w en ab les th e devi ce, pl aci ng i t i n t h e act i v e power m ode. aft e r power-up, a fal l i ng edge on chi p sel ect ( s ) is required prior to the start o f an y in stru ctio n . hold ( hold ) the hol d ( hold ) si gnal i s used t o pause any seri al com m uni cat i ons wi t h t h e devi ce wi t hout desel ect i ng t h e devi ce. duri ng t h e hol d condi t i on, t h e seri al dat a out put (q) i s hi gh i m pedance, and seri al dat a i nput (d) and seri al cl ock (c ) are don?t care. to start the hold condition, the device m u st be selected, with chip select ( s ) d r iv en lo w. write protect ( w ) thi s i nput si gnal i s used t o prot ect t h e m e m o ry agai nst wri t e i n st ruct i ons. w h en wri t e prot ect ( w ) is h e ld lo w, write i n st ruct i ons (w r s r , w r ite) are i gnored. no act i on on t h i s si gnal can i n t e rrupt a wri t e cy cl e t h at has al ready st art e d.
r1ex25002axx00a/r1ex25004axx00a rej03c0357-0002 rev. 0.02 jan.14 .2009 page 9 of 20 functional description status register the fol l o wi ng fi gure shows t h e st at us r e gi st er form at . the st at us r e gi st er cont ai ns a num ber of st at us and cont rol bi t s t h at can be read or set (as appropri a t e ) by speci fi c i n st ruct i ons. status register format 1 1 1 1 bp1 bp0 wel wip block protect bits write enable latch bits write in progress bits b0 b7 w i p b it: th e w r ite in pro g r ess (w ip) b it in d i cates wh eth e r th e m e m o ry is b u s y with a w r ite o r w r ite statu s reg i ster cycle. w el b it: th e w r ite en ab le latch (w el) b it in d i cates th e statu s o f th e in tern al w r ite en ab le latch . bp1, bp0 bits: the block protect (bp1, bp0) bits are non-vol atile. they define the size of the area to be protected ag ain s t w r ite in stru ctio n s . instructions each in stru ctio n starts with a sin g l e-b y te co d e , as su m m a rized in th e fo llo win g tab l e . if an in v a lid in stru ctio n is sen t (one not cont ai ned i n t h e fol l o wi ng t a bl e), t h e devi ce aut o m a t i cal l y desel ect s i t s el f. instruction set in stru ctio n d e s c r i p tio n in stru ctio n f o r m a t w r e n w r i t e e n a b l e 0 0 0 0 110 w r d i w r i t e d i s a b l e 0 0 0 0 100 rdsr read status register 0000 101 w r sr w r ite status register 0000 001 read read from memory array 0000 a011 w r it e w r ite to memory array 0000 a010 notes: 1. ? ? is don?t care. 2. ?a? is a 8 address on the r1ex25004a, and don?t care on the r1ex25002a.
r1ex25002axx00a/r1ex25004axx00a rej03c0357-0002 rev. 0.02 jan.14 .2009 page 10 of 20 write enable (wren): the w r ite enable latch (w el) bit m u st be set prior to each w r ite and w r sr inst ruction. the only way to do this is to sen d a w r ite en ab le in stru ctio n to th e d e v i ce. as sh o w n in th e fo llo win g fig u r e, to sen d th is in stru ctio n to th e d e v i ce, chip select ( s ) i s dri v en l o w, and t h e bi t s of t h e i n st ruct i on by t e are shi f t e d i n , on seri al dat a i nput (d). the devi ce t h en en ters a wait state. it waits fo r th e d e vice to be deselected, by chip select ( s ) bei ng dri v en hi gh. write enable (wren) sequence s w c d q instruction 01 2 3 4 5 6 high-z v ih v il v ih v il v ih v il v ih v il 7
r1ex25002axx00a/r1ex25004axx00a rej03c0357-0002 rev. 0.02 jan.14 .2009 page 11 of 20 write disable (wrdi): on e way o f resettin g th e w r ite en ab le latch (w el) b it is to sen d a w r ite disab l e in stru ctio n to th e d e v i ce. as sh o w n in th e fo llo win g fig u r e, to sen d th is in stru ctio n to th e d e v i ce, ch ip select ( s ) is d r iv en lo w, an d th e b its o f th e in stru ctio n by t e are shi f t e d i n , on seri al dat a i nput (d). the device then enters a wait state. it waits fo r t h e devi ce t o be desel ected, by chip select ( s ) bei ng dri v en hi gh. the w r ite en ab le latch (w el) b it, in fact, b eco m e s reset b y an y o f th e fo llo win g ev en ts: power-up w r di instruction execution w r sr in stru ctio n co m p letio n w r ite in stru ctio n co m p letio n w r ite prot ect ( w ) is d r iv en lo w write disable (wrdi) sequence s w c d q instruction 1 0 2 3 4 567 high-z v ih v il v ih v il v ih v il v ih v il
r1ex25002axx00a/r1ex25004axx00a rej03c0357-0002 rev. 0.02 jan.14 .2009 page 12 of 20 read status register (rdsr): the read status register (rdsr) instructi on allows the status register to be read . the status register m a y be read at an y tim e, ev en wh ile a w r ite o r w r ite statu s register cycle is in progress. w h en one of these cycles is in progress, it is recom m e nded t o check t h e w r i t e in progress (w ip) bi t before sendi ng a new i n st ruct i on t o t h e devi ce. it i s al so possi bl e t o read t h e st at us r e gi st er cont i nuousl y , as shown i n t h e fol l o wi ng fi gure. read status register (rdsr) sequence s w c d q status register out 01 2 3 4 5 6 7 0 1 2 3 4 5 6 77 8 9 10 11 12 13 14 15 high-z v ih v il v ih v il v ih v il v ih v il the st at us and cont rol bi t s of t h e status register are as follows: w i p b it: th e w r ite in pro g r ess (w ip) b it in d i cates wh eth e r th e m e m o ry is b u s y with a w r ite o r w r ite statu s reg i ster cycle. w h en set to 1, such a cycle is in progress. w h en reset to 0, no such cycles are in progress. w el b it: th e w r ite en ab le latch (w el) b it in d i cates th e statu s o f th e in tern al w r ite en ab le latch . w h en set to 1 , th e in tern al w r ite en ab le latch is set. w h en set to 0 , th e in tern al w r ite en ab le latch is reset an d n o w r ite o r w r ite statu s register instructions are accepted. bp1, bp0 bits: the block protect (bp1, bp0) bits are non-vol atile. they define the size of the area to be software p r o t ected ag ain s t w r ite in stru ctio n s . th ese b its are written with th e w r ite statu s reg i ster (w rsr) in stru ctio n . w h en one or bot h of t h e b l ock prot ect (b p1, b p 0) bi t s are set t o 1, t h e rel e vant m e m o ry area (as defi ned i n t h e st at us register form at table) becom e s protected agai nst w r i t e (w r i te) i n st ruct i ons. the b l ock prot ect (b p1, b p 0) bi t s can b e written p r o v i d e d th at th e hard ware pro t ected m o d e h a s n o t b een set.
r1ex25002axx00a/r1ex25004axx00a rej03c0357-0002 rev. 0.02 jan.14 .2009 page 13 of 20 write status register (wrsr): th e w r ite statu s reg i ster (w rsr) in stru ctio n allo ws n e w v a lu es to b e written to th e statu s reg i ster. befo re it can b e accepted, a w r ite enable (w ren) instruc tion m u st previously have been execute d. after the w r ite enable (w ren) i n st ruct i on has been decoded and execut e d, t h e devi ce set s th e w r ite en ab le latch ( w el). th e in stru ctio n seq u e n ce is shown i n t h e fol l o wi ng fi gure. the w r i t e st at us r e gi st er (w r s r ) i n st ruct i on has no effect on b6, b5, b4, b1 and b0 of t h e st at us r e gi st er. b6, b5 and b4 are always read as 0. chip select ( s ) m u st be dri v en hi gh aft e r t h e ri si ng edge of serial clo c k (c) th at latch e s in th e eig h t h b it o f th e d a ta by t e , and before t h e next ri si ng edge of seri al cl ock (c ). ot herwi s e, t h e w r i t e st at us r e gi st er (w r s r ) i n st ruct i on i s not execut e d. as soon as chi p sel ect ( s ) i s dri v en hi gh, t h e self-tim ed w r ite statu s reg i st er cycle (whose duration is t w ) is in itiated . w h ile th e w r ite statu s reg i ster cycle is in p r o g r ess, th e statu s reg i ster m a y still b e read to ch eck th e v a lu e o f th e w r ite in pro g r ess (w ip) b it. th e w r ite in pro g r ess (w ip) b it is 1 d u r in g th e self-tim ed w r ite statu s reg i ster cycle, an d is 0 wh en it is co m p leted . w h en th e cycle is co m p leted , w r ite en ab le latch ( w el) is reset. th e w r ite statu s reg i ster (w rsr) in stru ctio n allo ws th e u s er t o change t h e val u es of t h e b l ock prot ect (b p1, b p 0) bi t s , t o de fine the size of the area that is to be treated as read-only, as defi ned i n t h e st at us r e gi st er form at t a bl e. the cont ent s of b l ock prot ect (b p1, b p 0) bits are frozen at their current values ju st before the start of the execution of t h e w r i t e st at us r e gi st er (w r s r ) i n st ruct i on. the new, updat e d val u es t a ke effect at t h e m o m e nt of com p l e t i on of t h e execut i on of w r i t e st at us r e gi st er (w r s r ) i n st ruct i on. write status register (wrsr) sequence s w c d q status register in msb 01 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 high-z v ih v il v ih v il v ih v il v ih v il
r1ex25002axx00a/r1ex25004axx00a rej03c0357-0002 rev. 0.02 jan.14 .2009 page 14 of 20 read from mem o ry array (read): as sh o w n in th e fo llo win g fig u r e, to sen d th is in stru ctio n to th e d e v i ce, ch ip select ( s ) is first d r iv en lo w. th e b its o f t h e i n st ruct i on by t e and t h e address by t e s are t h en shi f t e d i n , on seri al dat a i nput (d). the addresses are l o aded i n t o an i n t e rnal address regi st er, and t h e by t e of dat a at t h at address i s shi f t e d out , on seri al dat a out put (q). the m o st si gni fi cant address (a8) shoul d be sent as fi ft h bi t i n t h e i n st ruct i on by t e . if chip select ( s ) co n tin u e s to b e d r iv en lo w, th e in tern al ad d r ess reg i ster is au to m a tically in crem en ted , an d th e b y te o f dat a at t h e new address i s shi f t e d out . w h en the highest address is reached, the address counter ro lls over to zero, allowing the read cycle to be continued indefinitely. the whole m e m o ry can, therefor e, be read with a single read instruction. the read cycle is term inated by dri v i ng chi p sel ect ( s ) hi gh. the ri si ng edge of t h e chi p sel ect ( s ) signal can occur at any tim e during the cycle. the addressed first byte can be any byte within any page. th e instruction is not accepted, an d is n o t ex ecu ted , if a w r ite cycle is currently in progress. read from memory array (read) sequence s w c d q 8-bit address data out 2 data out 1 01 2 3 4 5 6 7 a0 a1 a2 a3 a5 a6 a7 a8 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 high-z v ih v il v ih v il v ih v il v ih v il 0 1 2 3 4 5 6 77 instruction note: 1. depending on the memory size, as show n in the fo llow i ng table, the most signi ficant address bits are don?t care. address range bits dev i c e r 1 e x 2 5 0 0 4 a r1ex25002a address bits a8 to a0 a7 to a0 note: 1. a8 is don?t care on the r1ex25002a.
r1ex25002axx00a/r1ex25004axx00a rej03c0357-0002 rev. 0.02 jan.14 .2009 page 15 of 20 write to mem o ry array (write): as sh o w n in th e fo llo win g fig u r e, to sen d th is in stru ctio n to th e d e v i ce, ch ip select ( s ) is first d r iv en lo w. th e b its o f t h e i n st ruct i on by t e , address by t e , and at l east one dat a by t e are t h en shi f t e d i n , on seri al dat a i nput (d). th e in stru ctio n is term in ated b y d r iv in g ch ip select ( s ) hi gh at a by t e boundary of t h e i nput dat a . in t h e case of t h e fo llo win g fig u r e, th is o ccu rs after th e eig h t h b it o f th e d a ta b y te h a s b een latch e d in , in d i catin g th at th e in stru ctio n is bei ng used t o wri t e a si ngl e by t e . the sel f-t i m ed w r i t e cy cl e st art s , and cont i nues for a peri od t wc (as specified in ac ch aracteristics). at th e en d o f th e cycle, th e w r ite in pro g r ess (w ip) b it is reset to 0 . if, t hough, chi p sel ect ( s ) cont i nues t o be dri v en l o w, as shown i n t h e fol l o wi ng fi gure, t h e next by t e of t h e i nput dat a i s shi f t e d i n , so t h at m o re t h an a si ngl e by t e , st art i ng from t h e gi ven address t o wards t h e end of t h e sam e page, can be written in a sin g l e in tern al w r ite cycle. each t i m e a new dat a by t e i s shi f t e d i n , t h e l east si gni fi cant bi t s of t h e i n t e rnal address count er are i n crem ent e d. if t h e num ber of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the b e g i n n i n g o f th e p a g e , an d th e p r ev io u s d a ta th ere are o v e rwritten with th e in co m i n g d a ta. (th e p a g e size o f th ese devi ce i s 32 by t e s). the instruction is not accepted, and is not executed, under the following conditions: if th e w r ite en ab le latch (w el) b it h a s n o t b een set to 1 (b y ex ecu tin g a w r ite en ab le in stru ctio n j u st b e fo re) if a w r ite cycle is already in progress if t h e addressed page i s i n t h e regi on prot ect ed by t h e b l ock prot ect (b p1 and b p 0) bi t s . if w r ite protect ( w ) is lo w by te write (write) sequence (1 by te) s w c d q 8-bit address data byte 1 01 2 3 4 5 6 7 0 1 2 3 a5 a6 a7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 high-z v ih v il v ih v il v ih v il v ih v il 4 5 6 7 a0 a1 a2 a3 instruction a8 note: 1. depending on the memory size, as show n in addre ss range bits table, the most significant address bit is don?t care.
r1ex25002axx00a/r1ex25004axx00a rej03c0357-0002 rev. 0.02 jan.14 .2009 page 16 of 20 by te write (write) sequence (page) s w c d q 8-bit address data byte 1 01 2 3 4 5 6 7 0 1 2 3 a5 a6 a7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 high-z v ih v il v ih v il v ih v il v ih v il 4 5 6 7 a0 a1 a2 a3 instruction s w c d q data byte 3 data byte n 24 25 26 27 28 29 30 31 7 32 33 34 35 36 37 38 39 high-z v ih v il v ih v il v ih v il 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 data byte 2 a8 note: 1. depending on the memory size, as show n in addre ss range bits table, the most significant address bit is don?t care.
r1ex25002axx00a/r1ex25004axx00a rej03c0357-0002 rev. 0.02 jan.14 .2009 page 17 of 20 data protect the b l ock prot ect bi t s (b p1, b p 0) defi ne t h e area of m e m o ry that is protected against the execution of write cycle, as su m m a rized in th e fo llo win g tab l e. w h en w r ite protect ( w ) is d r iv en lo w, write to m e m o ry array (w rite) an d write statu s reg i ster (w rsr) are d i sab l ed , an d w el b it is reset. write protected block size statu s reg i ster b i ts a rray ad d r esses p r o t ected b p 1 b p 0 pro t ected b l o c k s r1ex25004a r1ex25002a 0 0 n o n e n o n e n o n e 0 1 u p p e r q u a r t e r 1 8 0 h ? 1f f h c0h ? ffh 1 0 u p p e r h a l f 1 0 0 h ? 1f f h 80h ? ffh 1 1 w h o l e memory 0 0 0 h ? 1f f h 00h ? ffh hold condition the hol d ( hold ) signal is used to pause any serial com m unicati ons with the device wit hout resetting the clocking sequence. duri ng t h e hol d condi t i on, t h e seri al dat a out put (q) i s hi gh i m pedance, and seri al dat a i nput (d) and seri al cl ock (c ) are don?t care. to ent e r t h e hol d condi t i on, t h e devi ce m u st be selected, with chip select ( s ) low. norm al l y , t h e devi ce i s kept sel ect ed, for t h e whol e durat i on of t h e hol d condi t i on. desel ect i ng t h e devi ce whi l e i t i s i n t h e hol d condi t i on, has t h e effect of reset t i ng t h e st at e of t h e devi ce, and t h i s m echani s m can be used i f i t i s requi red t o reset any processes t h at had been i n progress. the hol d condi t i on st art s when t h e hol d ( hold ) sig n a l is d r iv en lo w at th e sam e tim e as serial clock (c) already being l o w (as shown i n t h e fol l o wi ng fi gure). the hol d condi t i on ends when t h e hol d ( hold ) sig n a l is d r iv en h i g h at th e sam e tim e as serial clock (c) already being lo w. the fol l o wi ng fi gure al so shows what happens i f t h e ri si ng and fal l i ng edges are not t i m ed t o coincide with serial clock (c ) bei ng l o w. hold condition activ a tion c hold hold status hold status
r1ex25002axx00a/r1ex25004axx00a rej03c0357-0002 rev. 0.02 jan.14 .2009 page 18 of 20 notes data protection at v cc on/off wh e n v cc i s t u rned on or off, noi se on s i nput s generat e d by ext e rnal ci rcui t s (c pu, et c) m a y act as a t r i gger and t u rn t h e eepr o m t o uni nt ent i onal program m ode. to prevent t h i s uni nt ent i onal program m i ng, t h i s eepr o m have a power on reset funct i on. b e careful of t h e not i ces descri bed bel o w i n order for t h e power on reset funct i on t o operat e correctly. ? s shoul d be fi xed t o v cc duri ng v cc on/ off. low t o hi gh or hi gh t o l o w t r ansi t i on duri ng v cc on/ off m a y cause t h e t r i gger for t h e uni nt ent i onal program m i ng. ? v cc should be turned on/off after the eep rom is placed in a standby state. ? v cc shoul d be t u rned on from t h e ground l e vel (v ss ) i n order for t h e eepr o m not t o ent e r t h e uni nt ent i onal program m i ng m ode. ? v cc t u rn on speed shoul d be sl ower t h an 10 s/v. ? w h en w r sr or w r ite i n st ruct i on i s execut e d before v cc turns off, v cc should be turned off after waiting write cycle tim e (t w ).
r1ex25002axx00a/r1ex25004axx00a rej03c0357-0002 rev. 0.02 jan.14 .2009 page 19 of 20 package dimensions r1ex25002asa00a/r1ex25004asa00a (prsp0008df-b / previ ous code: fp-8dbv) prsp0008df-b p-sop8-3.9x4.89-1.27 a l e c b d e a b c x y h z l 2 1 1 e 1 mass[typ.] 0.08g 4.89 1.06 0.25 0 8 6.02 0.15 0.20 0.25 0.45 0.102 0 .14 0.254 3.90 0.406 0 .60 0 .889 1.73 reference symbol dimension in millimeters min n om max previous code jeita package code renesas code fp-8dbv 5.15 1 a p 0.35 0.40 6.20 5.84 1.27 0.10 0.69 index mark e 1 y xm p * 3 * 2 * 1 f 4 85 d e h a z b p terminal cross section ( ni/pd/au plating ) b c detail f 1 1 l l a note) 1. dimensions" * 1 (nom)"and" * 2" do not include mold flash. 2. dimension" * 3"does not include trim offset. e
r1ex25002axx00a/r1ex25004axx00a rej03c0357-0002 rev. 0.02 jan.14 .2009 page 20 of 20 r1ex25002ata00a/r1ex25004ata00a (ptsp0008jc-b / previous code: ttp-8dav) ptsp0008jc-b p-tssop8-4.4x3-0.65 a l e c b d e a b c
revision history r1ex25002axx00a/r1ex25004axx00a data sheet contents of modification rev. date page description 0.01 jan.25, 2008 ? initial issue 0.02 jan.14, 2009 p1 p3 p4 p5/p6 features endurance cycles change 10 6 cycles to 1,000k cycles @25 c. data retentions years change 10 years to 100 years @25 c. capacitance new is described. memory cell characteristics new is described. dc characteristics output voltage v oh1, v oh2 test conditions change i ol to i oh. ac characteristics erase/write enduranc e is deleted. notes1. change not 100% tested. notes3 deleted.
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